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<h4 class="subsection" id="Order-of-Allocation-of-Registers"><span>18.7.2 Order of Allocation of Registers<a class="copiable-link" href="#Order-of-Allocation-of-Registers"> &para;</a></span></h4>
<a class="index-entry-id" id="index-order-of-register-allocation"></a>
<a class="index-entry-id" id="index-register-allocation-order"></a>

<p>Registers are allocated in order.
</p>
<dl class="first-deffn first-defmac-alias-first-deffn">
<dt class="deffn defmac-alias-deffn" id="index-REG_005fALLOC_005fORDER"><span class="category-def">Macro: </span><span><strong class="def-name">REG_ALLOC_ORDER</strong><a class="copiable-link" href="#index-REG_005fALLOC_005fORDER"> &para;</a></span></dt>
<dd><p>If defined, an initializer for a vector of integers, containing the
numbers of hard registers in the order in which GCC should prefer
to use them (from most preferred to least).
</p>
<p>If this macro is not defined, registers are used lowest numbered first
(all else being equal).
</p>
<p>One use of this macro is on machines where the highest numbered
registers must always be saved and the save-multiple-registers
instruction supports only sequences of consecutive registers.  On such
machines, define <code class="code">REG_ALLOC_ORDER</code> to be an initializer that lists
the highest numbered allocable register first.
</p></dd></dl>

<dl class="first-deffn first-defmac-alias-first-deffn">
<dt class="deffn defmac-alias-deffn" id="index-ADJUST_005fREG_005fALLOC_005fORDER"><span class="category-def">Macro: </span><span><strong class="def-name">ADJUST_REG_ALLOC_ORDER</strong><a class="copiable-link" href="#index-ADJUST_005fREG_005fALLOC_005fORDER"> &para;</a></span></dt>
<dd><p>A C statement (sans semicolon) to choose the order in which to allocate
hard registers for pseudo-registers local to a basic block.
</p>
<p>Store the desired register order in the array <code class="code">reg_alloc_order</code>.
Element 0 should be the register to allocate first; element 1, the next
register; and so on.
</p>
<p>The macro body should not assume anything about the contents of
<code class="code">reg_alloc_order</code> before execution of the macro.
</p>
<p>On most machines, it is not necessary to define this macro.
</p></dd></dl>

<dl class="first-deffn first-defmac-alias-first-deffn">
<dt class="deffn defmac-alias-deffn" id="index-HONOR_005fREG_005fALLOC_005fORDER"><span class="category-def">Macro: </span><span><strong class="def-name">HONOR_REG_ALLOC_ORDER</strong><a class="copiable-link" href="#index-HONOR_005fREG_005fALLOC_005fORDER"> &para;</a></span></dt>
<dd><p>Normally, IRA tries to estimate the costs for saving a register in the
prologue and restoring it in the epilogue.  This discourages it from
using call-saved registers.  If a machine wants to ensure that IRA
allocates registers in the order given by REG_ALLOC_ORDER even if some
call-saved registers appear earlier than call-used ones, then define this
macro as a C expression to nonzero. Default is 0.
</p></dd></dl>

<dl class="first-deffn first-defmac-alias-first-deffn">
<dt class="deffn defmac-alias-deffn" id="index-IRA_005fHARD_005fREGNO_005fADD_005fCOST_005fMULTIPLIER"><span class="category-def">Macro: </span><span><strong class="def-name">IRA_HARD_REGNO_ADD_COST_MULTIPLIER</strong> <var class="def-var-arguments">(<var class="var">regno</var>)</var><a class="copiable-link" href="#index-IRA_005fHARD_005fREGNO_005fADD_005fCOST_005fMULTIPLIER"> &para;</a></span></dt>
<dd><p>In some case register allocation order is not enough for the
Integrated Register Allocator (<abbr class="acronym">IRA</abbr>) to generate a good code.
If this macro is defined, it should return a floating point value
based on <var class="var">regno</var>.  The cost of using <var class="var">regno</var> for a pseudo will
be increased by approximately the pseudo&rsquo;s usage frequency times the
value returned by this macro.  Not defining this macro is equivalent
to having it always return <code class="code">0.0</code>.
</p>
<p>On most machines, it is not necessary to define this macro.
</p></dd></dl>

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